DMA Controller 8257

DMA Controller 8257

DMA stands for direct memory access, thus 8257 is a controller chip required whenever we want direct memory access of some other device.

Three Transaction Methods

• Programmed IOs (like 8255 port used without handshake and Intr signals)
• Interrupt Driven IOs (like 8255 port used without handshake and Intr signals)
• DMA Transactions using a DMAC

Direct Memory Access Control (Peripheral Transactions Server) IOs

• Controller or server sends hold request for processor to grant on acknowledgement, the access to address and data buses, IORD, IOWR, MEMRD, MEMWR and IO buses.
• Once programmed for address of RAM block for transfer and for data counts of IO transactions with RAM, interrupts only at the end of a block transaction or last transaction.

BLOCK DIAGRAM

8257 Four Channel DMAC Features

• Four channels
• Priority Resolution support
• TC output and Mark output (after 126 bytes transfer) for interrupts to processor for attention
• Auto-load on TC mode support for repeat transactions without reprogramming TC and MAR and mode
• TTL level inputs/outputs compatible with INTEL families

Programming the 8257

• Each channel has 16 bit register with an access address (write LSB and then MSB at that address to program
• Each channel has 16 bit register for TC register (written LSB and then MSB)
• A3 = 0 for selecting a channel’s address and TC registers
• 0000 means ch0 MAR address, 0001TC address
• 0010 means ch1 MAR address, 0011TC address
• 0100 means ch2 MAR address, 0101TC address
• 0110 means ch1 MAR address, 0111TC address
• A3 = 1, IORD = 0 for selecting status register

PPI 8255

Programmable Priority Interface 8255

The 8255A programmable peripheral interface (PPI) implements a general-purpose I/O interface to connect peripheral equipment to a microcomputer system bus.

Features

• Three 8-bit Peripheral Ports – Ports A, B, and C
• Three programming modes for Peripheral Ports: Mode 0 (Basic Input/Output), Mode 1 (Strobed Input/Output), and Mode 2 (Bidirectional)
• Total of 24 programmable I/O lines
• 8-bit bidirectional system data bus with standard microprocessor interface controls

MODES

There are 3 basic modes of operation under which the ports can function.

• Mode 0 – Basic Input/Output
• Mode 1 – Strobed Input/Output (Not used by SVI)
• Mode 2 – Bi-Directional Bus (Not used by SVI)

Accessing Ports

The ports may be accessed separately by the CPU.

• Port A is accessed using port 98H
• Port B is accessed using port 99H
• Port C is accessed using port 96H

Using the 8255 Ports

WRITE

1)    Make sure the port is operating as output. (This is done by sending a control byte to port 97H).

2)    Write the data to the port.

3)    Return the port to it’s original I/O Status.

READ

1)   Make sure the port is operating as input. (This is done by sending a control byte to port 97H).

2)   Read the data from the port.

3)   Return the port to it’s original I/O Status.

USART 8251

USART 8251

• USART 8251 or universal synchronous and asynchronous receiver and transmitter.
• The USART chip integrates both a transmitter and a receiver for serial-data communication based on the RS-232 protocol.
• The Intel 8251 chip integrates a standard (8-bit) microprocessor bus interface, one serial transmitter, and one serial receiver.
• A few additional control lines are provided for modem-control and efficient handshaking or interrupts.

BLOCK

The bus-interface consists of the bidirectional 8-bit data-bus (lines D7..D0) and the read/write control-logic with the following inputs:

  DATA (D7..D0)        8-bit bidirectional data-bus
  RESET                    active-high reset input
  nCS                         chip select input (active low)
  CnD                          command (high) or data (low) selection input
  nRD                         read enable input (active low)
  nWR                        write enable input (active low)

The transmitter logic

nTXC                         transmitter clock input

TXD                           data output

TXE (or TXEMPTY)   Status output

TXRDY                      Status output

The receiver logic

RXC                          receiver clock input,

RXD                         data input,

RXRDY                     status output

SYNDET/BD              programmable select line

Modem control logic

nDTR                         (data transmit ready) Output lines

nRTS                         (ready to transmit)

nCTS                         (clear to send) Input lines

nDSR                        (data send ready) Input lines

Command words

The chip contains seven user-visible registers, five of which can only be written, and two of which can only be read.

  mode register          sync/async operation mode and parameters
  command register    enable/disable and error resetting
  sync 1 character     8-bit dataword (sync mode only)
  sync 2 character      8-bit dataword (sync mode only)
  transmit buffer         8-bit register for outgoing data
  receive buffer          8-bit register with incoming data
  status register                several status and error bits

PIC 8259

Programmable Interrupt Controller 8259

PIC resolves the interrupt according to the priority level they have. It can be configured as master slave configuration so as to process several interrupt requests.

Internal architecture

• Data bus buffer and read-write logic:
• Interrupt mast register (IMR):
• Interrupt request register (IRR):
• Interrupt service register
• Priority resolver
• Cascade buffer comparator

Interrupt vectors and the 8259 PIC

Priority in the 8259

• 8259 supports several priority schemes

• On PC’s the 8259 uses the simplest form of fixed priorities

• Each IRQ has a fixed priority

• Lower IRQs has higher priority

• The timer interrupt (IRQ0) has lower priority than any other IRQ

• If you really need higher priority than the timer (e.g. connecting a nuclear reactor to your microprocessor) it is possible to use a NMI (non-maskable interrupt)

• NMI has the highest priority among all hardware interrupts and cannot be disabled by the program

Timer/counter 8253/8254

Timer / Counter 8253/8254

8253/54 will count out the delay and interrupt the CPU when it has completed its tasks. It is easy to see that the software overhead is minimum and that multiple delays can be easily be maintained by assignment of priority levels.

• The 8253/54 includes three identical 16 bit counters that can operate independently.
• 16-bit count is loaded in its register and, on command, it begins to decrement until it reaches 0.
• At the end of the count, it generates a pulse that can be used to interrupt the CPU.
• The counter can count either in binary or BCD.
• In addition, a count can be read by the CPU while the counter is decrementing.

• The 8254 is a superset of 8253. The functioning of these two ICs are almost similar along with the pin configuration. Only the differences are :

Features:

• Three independent 16-bit down counters.
• Three counters are identical presettable, and can be programmed for either binary or BCD count.
• Counter can be programmed in six different modes. Compatible with all Intel and most other microprocessors.
• 8254 has powerful command called READ BACK command

Pin diagram of 8254

Control word

BCD            – For BCD counting

M₀,M₁,M₂ – For defining the operation mode

RW₀,RW₁ – Either for read or write operation

SC₀,SC₁ – To select the counters

Microcontroller : 8051

Microcontrollers : 8051

• A highly integrated chip that contains all the components comprising a controller.
• Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers.
• Unlike a general-purpose computer, which also includes all of these components, a microcontroller is designed for a very specific task
  • To control a particular system.
  • Cuts down on production costs.
    • Microcontrollers are sometimes called embedded microcontrollers.

8051

• The Intel 8051 is a Harvard architecture, single chip microcontroller (µC) which was developed by Intel in 1980 for use in embedded systems.
• More than 20 independent manufacturers including Atmel, Infineon Technologies, Maxim Integrated Products, NXP, Nuvoton, ST Microelectronics, Silicon Laboratories, Texas Instruments and Cypress Semiconductor.
• Intel’s official designation for the 8051 family of µCs is MCS 51.

Important features and applications

• It provides many functions (CPU, RAM, ROM, I/O, interrupt logic, timer, etc.) in a single package
• 8-bit ALU, Accumulator and 8-bit Registers; hence it is an 8-bit microcontroller
• 8-bit data bus – It can access 8 bits of data in one operation
• 16-bit address bus – It can access 2¹⁶ memory locations – 64 KB (65536 locations) each of RAM and ROM
• On-chip RAM – 128 bytes (data memory)
• On-chip ROM – 4 kByte (program memory)
• Four byte bi-directional input/output port
• UART (serial port)
• Two 16-bit Counter/timers
• Two-level interrupt priority
• Power saving mode

Memory Architecture

The 8051 has four distinct types of memory –

• internal RAM
• special function registers
• program memory
• external data memory

Instruction set

The 8051 instruction set offers several addressing modes, including

• direct register, using ACC (the accumulator) and R0-R7
• direct memory, which access the internal RAM or the SFR’s, depending on the address
• indirect memory, using R0, R1, or DPTR to hold the memory address. The instruction used may vary to access internal RAM, external RAM, or program memory.
• individual bits of a range of IRAM and some of the SFR’s

Related processors

The 8051’s predecessor, the 8048, was used in the keyboard of the first IBM PC, where it converted keypresses into the serial data stream which is sent to the main unit of the computer. The 8048 and derivatives are still used today^[update] for basic model keyboards.

·       There are other related MCS-51 microcontrollers

o      8052

o      8032

o      8031

o      8751

And many more….

Pentium Processor

PENTIUM Processors

Intel Pentium processors arrived on the tech scene in 1993.

Their main features are :

• superscalar architecture
• fast processing
• speedy data transfers
• Pipeline Architecture
• Branch Target Buffer
• Dual 8-KB On-Chip Caches
• Write-Back Cache
• 64-Bit Bus

• These facts quickly revolutionized the industry, making the phrase “multi-tasking” a household word.
• Since then, designers have improved on the Pentium processors :
• Intel Pentium 2
• Intel Pentium 3
• Intel Pentium 4
• Intel Pentium D.

MODES

The Pentium processor has two primary operating modes and a “system management mode.”

• The operating mode determines which instructions and architectural features are accessible.
• These modes are:
  • · Protected Mode
  • · Real-Address Mode (also called “real mode”)
  • System Management Mode

Features

• The Pentium 3 processor featured improved speed and caching capabilities. and lower power consumption.
• The Pentium 4 processor appeared in 2000.
• Its NetBurst micro-architecture uses a deeper instruction pipeline, meaning a huge increase in processor speeds.
• However, both the Pentium 3 processor and the Pentium 4 processor are single-core processors, and have been superseded in the industry by faster, dual-core processing units, such as the Intel Pentium D and AMD’s Athlon.

WHY PENTIUM III or PENTIUM IV ?

1. You use your computer primarily for email and word processing, rather than gaming or creating 3D graphics.

2. You don’t need to transfer huge amounts of data quickly (e.g. downloading software from the Internet).

3. You want to save money on the processing unit and invest in peripherals or software.

Changing World

• MAJC (pronounced “magic”) is an acronym for “Microprocessor Architecture for Java Computing.”
• MAJC is a microprocessor architecture designed to meet the broadband demands of the 21st century.

Microprocessors 8085 & 8086

Microprocessors : 8085 & 8086

A microprocessor is an electronic device that reads instructions from memory, accepts binary data and provides output after processing data according to the instructions.

8085

8085 is a 8-bit microprocessor. Here the data is usually 8 bit and the address is 16 bit. Let’s analyze the each and every components of 8085 microprocessor.
1) Register section
2) ALU
3) The buses
4) Timing & Control unit

1. 1. Register section:
   It consists of number of registers for storing data and addresses. It can be of two types:

a)   General purpose registers : B, C, D, E, H and L

b) Special purpose registers

Accumulator (A) – It is an 8 bit register which is used for storing the operands or data during execution.

Program counter (PC) – It is a 16 bit register used to store the memory address of the next instruction to be executed.

Index register – This is used for addressing index addressing mode.

Status register – It stores the present status of the microprocessor after any arithmetic and logical operation.

Stack pointer – It is a 16 bit register used to initialize the stack.

Instruction register – It is a 8 bit register that stores the instruction fetched from memory

2) Arithmetic and Logical Unit (ALU):

It performs arithmetic and logical operations. Addition, subtraction, multiplication ,division, AND, OR, XOR, NOT, shift and rotate operations are done by ALU.

3) The Buses:

It is the interface section for communication between processor and external devices. There are 3 buses :

a)    Address bus – It carries the address of the instruction. It is 16 bit wide.

b)    Data bus – It carries the data & 8 bit wide and bidirectional.

c)    Control bus – It is used to send control signals to different units.

4) Timing & Control unit:

It generates the clock signals and control signals for communication between processor and peripheral devices.

8086

• The 8086 (officially called iAPX 86) is a 16-bit microprocessor chip designed by Intel in 1978, which gave rise to the x86 architecture.
• The 8086 was an ill-conceived attempt to provide an address space larger 64K bytes without actually incurring the costs of a larger architecture.
• The 8086 is basically a 16/16 architecture.
• It has following parts :
  • 16-bit program counter
  • 16-bit ALU
  • Four 16-bit general purpose registers
  • Some 16-bit index registers.
  • Four 16-bit segment registers.
• The 8086 performs all computation and data transfer in 16-bit arithmetic, with one exception.

8086 memory

• Memory is also byte-addressable.
  • The original 8086 had a 20-bit address bus that could address just 1MB of main memory.
  • Newer CPUs can access 64GB of main memory, using 36-bit addresses.
• Since the 8086 was a 16-bit processor, some terms are different.
  • A word in the 8086 world is 16 bits, not 32 bits.
  • A 32-bit quantity is called a double word instead.
  • Data does not have to be aligned. Programs can easily access data at any memory address, although performance may be worse.

Microprocessors and History

Microprocessors & History

Microprocessors contain core essentials of a computer system.

• Memory unit
• ALU
• Control unit
• Interrupt / Exception controller
• Internal cache

History of the Microprocessor

• In the year 1969, 4004 instruction set had been defined as a computer terminal corporation, also known as the (CTC).

• Hoff and a man by the name of Stan Mazor put the whole processor on one chip. The MCS-4 was made in April of 1972.

• Intel 8080 was developed in April of 1972. It was not available to customers at this time because of the design chip into the products and wasn’t ready.

• In 1978 Intel produced the first ever 16 bit processor the “8086” it was well-matched with the 8080, the 8086 was the most effective processor thus far.

Thus the series of evolution of Microprocessors includes (intel history):

4004 – 4040 – 8008 – 8080 – 8085 – 8086 – 8088 – 80186 – 80188 – 80286 – 80386DX – 80386SX – 80486DX – 80486SX – Pentium Processors

Competitors and the early years

• The second processor was available late in the year of 1972 developed by Rockwell. In 1974 Texas Instrument came out with the TMS1000 which was the first microprocessor to contain its very own RAM and ROM on chip.
• The success of the Intel 808 Zilog and Motorola, made the two produce competing chips.
• Intel’s very first microprocessor contained so much processing power that it was considered the “most powerful” computer in the world at the time.
• The Intel Pentium processor was released in 1993 making it the first available microprocessor capable of executing two instructions for every clock cycle. Intel’s serious competitor today is the AMD (Advanced Micro Devices).

RISC

In the 1980s and 1990s RISC (Reduced Instruction Set Computer) made its appearance. It was made for Unix workstations and purpose machines, but today are widespread in all roles set aside desktop computers. RISC today designs are based on MIPS, PowerPC and ARM for majority of computing devices.

Facts

• 44 Billion dollars worth of Microprocessors were made in 2003 as well as sold. Most was spent on laptop and or desktop computers it takes about 0.2 % of the CPU’s sold.

• Almost 56% of CPUs sold are 8 bit microcontrollers.

Less the 10 % of CPUs sold are 32 bit or more. Most are sold in house hold appliances such as vacuums, TVs, Microwaves, toasters and so forth.

PLD

PLD

• Any digital logic design can be done using PLDs.
• PLD stands for programmable logic devices
• Most anything found in your TTL Data book can be replaced with your own, PERSONALIZED, programmable logic device.

PLD Applications

• Glue Logic

• State Machines

• Synchronization

• Decoders

• Counters

• Bus Interfaces

• Parallel-to-Serial

• Serial-to-Parallel

• Subsystems

• Many Others

Why PLDs?

• Increased Integration.

• Lower Power.

• Improved Reliability.

• Lower Cost.

• Easier To Use!

• Easier to Change.

PLD Design Process

Following figure shows the PLD design process :



Classification of PLD :

1. Simple programmable logic array
   1. Programmable logic array
   2. Programmable array logic
   3. Generic array logic
2. Complex Programmable logic devices (CPLD)
3. Field Programmable gate arrays (FPGA)

Programmable logic arrays

These are having both the AND & OR array as a programmable unit.

Programmable array logic

In this AND array is programmable but the OR array is fixed.

Generic array logic

• The GAL has a reprogrammable AND array, fixed OR array with programmable output logic.
• These contain one or more PAL like structures but these are reprogrammable.

Field Programmable gate arrays

• These have the ability to be programmed for the specific function by the user instead of the manufacturer.
• It has large no. of input and output capability.
• The basic unit of FPGA is the configurable logic blocks (CLBs).

Complex programmable logic devices

• These have also large number of input-output capability but lesser than the FPGA.
• The basic unit of the CPLD is the macro cell, which is the CPLD implementation of the CLBs.
• The device can be reprogrammed by simply changing the configuration of data stored in the memory.