PLD

PLD

• Any digital logic design can be done using PLDs.
• PLD stands for programmable logic devices
• Most anything found in your TTL Data book can be replaced with your own, PERSONALIZED, programmable logic device.

PLD Applications

• Glue Logic

• State Machines

• Synchronization

• Decoders

• Counters

• Bus Interfaces

• Parallel-to-Serial

• Serial-to-Parallel

• Subsystems

• Many Others

Why PLDs?

• Increased Integration.

• Lower Power.

• Improved Reliability.

• Lower Cost.

• Easier To Use!

• Easier to Change.

PLD Design Process

Following figure shows the PLD design process :



Classification of PLD :

1. Simple programmable logic array
   1. Programmable logic array
   2. Programmable array logic
   3. Generic array logic
2. Complex Programmable logic devices (CPLD)
3. Field Programmable gate arrays (FPGA)

Programmable logic arrays

These are having both the AND & OR array as a programmable unit.

Programmable array logic

In this AND array is programmable but the OR array is fixed.

Generic array logic

• The GAL has a reprogrammable AND array, fixed OR array with programmable output logic.
• These contain one or more PAL like structures but these are reprogrammable.

Field Programmable gate arrays

• These have the ability to be programmed for the specific function by the user instead of the manufacturer.
• It has large no. of input and output capability.
• The basic unit of FPGA is the configurable logic blocks (CLBs).

Complex programmable logic devices

• These have also large number of input-output capability but lesser than the FPGA.
• The basic unit of the CPLD is the macro cell, which is the CPLD implementation of the CLBs.
• The device can be reprogrammed by simply changing the configuration of data stored in the memory.