PLD

Posted on August 15, 2010 by masherz

PLD

Any digital logic design can be done using PLDs.
PLD stands for programmable logic devices
Most anything found in your TTL Data book can be replaced with your own, PERSONALIZED, programmable logic device.

PLD Applications

• Glue Logic

• State Machines

• Synchronization

• Decoders

• Counters

• Bus Interfaces

• Parallel-to-Serial

• Serial-to-Parallel

• Subsystems

• Many Others

Why PLDs?

• Increased Integration.

• Lower Power.

• Improved Reliability.

• Lower Cost.

• Easier To Use!

• Easier to Change.

PLD Design Process

Following figure shows the PLD design process :

Classification of PLD :

Simple programmable logic array
1. Programmable logic array
2. Programmable array logic
3. Generic array logic
Complex Programmable logic devices (CPLD)
Field Programmable gate arrays (FPGA)

Programmable logic arrays

These are having both the AND & OR array as a programmable unit.

Programmable array logic

In this AND array is programmable but the OR array is fixed.

Generic array logic

The GAL has a reprogrammable AND array, fixed OR array with programmable output logic.
These contain one or more PAL like structures but these are reprogrammable.

Field Programmable gate arrays

These have the ability to be programmed for the specific function by the user instead of the manufacturer.
It has large no. of input and output capability.
The basic unit of FPGA is the configurable logic blocks (CLBs).

Complex programmable logic devices

These have also large number of input-output capability but lesser than the FPGA.
The basic unit of the CPLD is the macro cell, which is the CPLD implementation of the CLBs.
The device can be reprogrammed by simply changing the configuration of data stored in the memory.

Semiconductor Memories

Posted on August 15, 2010 by masherz

SEMICONDUCTOR MEMORIES

Semiconductor Memories are classified according to the type of data storage and the type of data access mechanism into the following two main groups:

• Non-volatile Memory (NVM) also known as Read-Only Memory (ROM) which retains information when the power supply voltage is off.

Mask programmed ROM. contents of the memory is programmed during fabrication,
Programmable ROM (PROM). contents are written in a permanent way by burning out internal interconnections (fuses).
Erasable PROM (EPROM). Data is stored as a charge on an isolated gate capacitor (“floating gate”).
Electrically Erasable PROM (EEPROM) also known as Flash Memory. The contents can be re-programmed by applying suitable voltages to the EEPROM pins.

• Read/Write (R/W) memory, also known as Random Access Memory (RAM). From the point of view of the data storage mechanism RAM are divided into two main groups:

Static RAM, where data is retained as long as there is power supply on.
Dynamic RAM, where data is stored on capacitors and requires periodic refreshment.

4-by-4 NOR ROM array 3-by-4 NAND ROM array

The drawback of the NAND ROM is that they are usually slower comparing with the corresponding NOR ROM, because of a significant number of serially connected nMOS transistors between the bit line and the ground.

Structure of the CMOS memory cell

Static Read/Write (or Random Access) memory (SRAM) is able to read and write data into its memory cells and retain the memory contents as long as the power supply voltage is provided.

Dynamic Read-Write Memory (DRAM)

In the static CMOS read-write memory data is stored in six-transistor cells. Such a memory is fast and consumed small amount of static power.

In a dynamic RAM binary data is stored as charge in a capacitor.

Fig : One transistor DRAM cell

Hazards & Faults

Posted on August 15, 2010 by masherz

HAZARDS & FAULTS

A logic circuit is expected to give logic-1 output momentarily becomes logic-0 because of finite propogation delay of various gates, this unwanted switching transient is called HAZARD.

Hazards in combinational logic circuits

When the input to a combinational circuit changes, unwanted switching transients may appear at the logic circuit output.

Classification of HAZARDS

Static Hazards

a) static-1 hazard

b) static-0 hazard

Dynamic Hazard
Essential Hazard

Stati-1 hazard

In response to an i/p change, a logic circuit may go to 0, when it should remain constant 1.

Static-0 hazard

In response to an input change, a logic circuit may go to 1 when it should remain constant at 0.

Dynamic hazard

When o/p of logic circuit is changed from 0 to 1 to 0 or 1 to 0 to 1. These two o/p may change more number of times, this transient is called dynamic hazard.

Prevention of HAZARDS in logic gates

Static & Dynamic hazards can be prevented by adding extra gates in the circuit as the redundant term.

Essential Hazards

The static and dynamic hazards occur in combinational as well as sequential circuits but the essential hazards occur in sequential circuits only.

The only way to protect essential hazard is to introduce the same amount of delay in all paths from input to output.

FAULT DETECTION

Fault occurs due to wrong connection, cable fault or improper soldering.

Types of FAULTS

Stuck at zero (S-A-0) : Input line is grounded by a faulty connection.
Stuck at one (S-A-1) : Input line is shorted to Vcc by a faulty connection.

FAULT Detection methods :

Fault table method
Boolean difference method
Path-sensitizing method
Equivalent normal form (ENF) method
Structure and parity observing output function method
Multiple – level fault detection

Fault table method

A fault table is formed that shows all possible faults and minimum set of tests to be performed on a combinational logic circuit to detect these faults.

If a redundant circuit further minimization is not possible and if a fault occurs in such a line, it can not be detected.

Boolean Difference method

This method is based on extracting the Boolean difference of the line (input) which is common to one or more gates.

Path sensitivity method

In this method we sensitize our signal flow path in such a way that any change in an output or interim output lines gets transmitted at very fast rate to the output.

ENF Method

An SOP expression showing the relation between the output of each gate to its inputs, while retaining the identity of each gate and defining the signal flow path is known as the ENF method.

SPOOF Method

SPOOF is similar to ENF method of fault detection but requires lesser number of tests and thus much efficient than ENF method.

Multilevel fault detection Method

Fault detection in multilevel circuit follows the same procedure as above.

Logic Family

Posted on August 15, 2010 by masherz

LOGIC FAMILIES

The types of logic devices are classified in “families”, of which the most important are TTL and CMOS. The main families are:

TTL (Transistor-Transistor Logic) made of bipolar transistors.
CMOS made from MOSFETs

(Complementary Metal Oxide Semiconductor)

ECL (Emitter Coupled Logic) for extremely high speeds
NMOS, PMOS for VLSI large scale integrated circuits.

TTL Logic Family

The transistor-transistor-logic (TTL) family was developed in the use of transistor switches for logical operations and defines the binary values as:

0 V to 0.8 V = logic 0

2 V to 5 V = logic 1

They are inexpensive, but draw a lot of power and must be supplied with +5 volts.
Individual gates may draw 3 to 4 mA.
The low power Schottky versions of TTL chips draw only 20% of the power, but are more expensive.
Part numbers for these chips have LS in the middle of them.

CMOS Logic Family

CMOS chips are much lower in power requirements (drawing about 1 mA) and operate with a wide range of supply voltages (typically 3 to 18 volts).

The CMOS model number will have a C in the middle of it, e.g., the 74C04 is the CMOS equivalent to the TTL 7404.
A big drawback is extreme sensitivity to static electricity – they must be carefully protected from static discharges.

NMOS and PMOS Logic ICs

P- and N-channel Metal Oxide Semiconductors (PMOS and NMOS) offer the advantage of higher component density than TTL chips.

There are not nearly so many TTL equivalents (CMOS family does much better here).
They are sensitive to damage from electrical discharge.

Component Designations

Integrated circuits in the TTL logic family have part numbers which are four to five digit numbers.

With the introduction of other types of construction of devices, letters were added to center of the numbers to remind the user that basic TTL chips are not being used.

7400	the TTL designation
74C00	the CMOS equivalent
74LS00	the low-power Schottky implementation

Registers & Counters

Posted on August 15, 2010 by masherz

REGISTERS & COUNTERS

Register – is a group of flip-flops. Its basic function is to hold information within a digital system so as to make it available to the logic units during the computing process. However, a register may also have additional capabilities associated with it.

Counter – is essentially a register that goes through a predetermined sequence of states. The gates in the counter are connected in such a way as to produce the prescribed sequence of binary states.

REGISTERS

Register with Parallel Load

If all the bits in a register are loaded at the same time, the loading is done in parallel.

Shift Registers

Registers capable of shifting their binary contents in one or both directions. A unidirectional 4-bit shift register that uses only flip-flops is as follows:

Universal Shift Register

A second general classification of shift registers consists of bidirectional shift registers.These type of registers are capable of shifting their contents either left or right depending upon the signals present on appropriate control input lines.

COUNTERS

A counter is an example of a register. Its primary function is to produce a specified output pattern sequence.

Each node Si denotes the states of the counter and the arrows in the graph denote the order in which the states occur. Counters are available in two categories: ripple counters and synchronous counters.

RIPPLE COUNTERS

In a ripple counter, the flip-flop output transition serves as a source for triggering other flip-flops.

Synchronous Binary Counters

The settling time problem associated with ripple counters is avoided in synchronous counters. In these counters, the count pulses are applied directly to the control inputs C of all flip-flops.

Ring Counter

It is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals.

Johnson Counter

An interesting variation of the ring counter is obtained if, instead of the Q output we take the Q′ of the last stage and feed it back to the first stage.

Sequential Circuits

Posted on August 15, 2010 by masherz

SEQUENTIAL CIRCUITS

Sequential circuits are combinational circuits with a feedback element in their circuitry path that includes one or more memory elements.

Latch A latch is a 1-bit memory element. You can capture a single bit in a latch at one instant and then use it later.

for example, when adding numbers you can capture the carry-out in a latch and use it as a carry-in in the next calculation.

Register The register is just m latches in a row and is able to store an m-bit word that is, the register is a device that stores one memory word. A computer’s memory is just a very large array of registers.

Shift register A shift register is a special-purpose register that can move the bits of the word it holds left or right; for example the 8-bit word 00101001 can be shifted left to give 01010010.

Counter A counter is another special-purpose register that holds an m-bit word. However, when a counter is triggered (i.e. clocked) its contents increase by 1

for example, if a counter holding the binary equivalent of 42 is clocked, it will hold the value 43. Counters can count up or down, by 1 or any other number, or they can count through any arbitrary sequence.

State machines A state machine is a digital system that moves from one state to another each time it is triggered. Ultimately, the computer itself is a nothing more than a state machine controlled by a program and its data.

SR LATCH

The SR latch, made of two 2-input NOR gates, which is the simplest interesting sequential circuit.

SYNCHRONOUS SEQUENTIAL LOGIC

The circuits considered so far are examples of asynchronous sequential logic circuits.

ASYNCHRONOUS SEQUENTIAL LOGIC

In an asynchronous circuit, the state of the circuit, ie the value on the fed back signal(s), can change at any time in response to an input change. Asynchronous circuits are tricky to design,

The general way of representing the sequential circuit is shown in the following figure :

To check a sequence of symbols, the circuit is started in the state corresponding to the DFA start state, and the input symbol sequence is presented on the inputs to the circuit, one symbol per clock cycle. The circuit moves between states, one state transition per clock cycle, and the output indicates at any time whether or not it is in an accepting state.

Combinational Logic Circuits

Posted on August 13, 2010 by masherz

Combinational Logic Circuits

Any Boolean expression can be converted to a logic circuit made up of AND, OR and NOT gates.

Simplifying Boolean expression

SOP Form

The sum of products is one of two standard forms for Boolean expressions.

sum-of-products-expression = s-term+ s-term… + s-term
S-term = Literal. Literal. Literal

Example. XYZ + XZ + XY + XYZ

A minterm is a sum term that contains every variable, in either complemented or uncomplemented form.

Example. In expression above, XYZ is minterm, but XZ is not sum of minterms expression is a sum of products expression in which every term is a minterm.

Example. XYZ + XYZ + XYZ + XYZ is sum of minterms expression that is equivalent to expression above.

Shorthand: List minterms numerically. e.g. £m(1,3,6,7)

Karnaugh Map

A Karnaugh map is a graphical tool for assisting in the general simplification procedure.

Two variables K-Map Three Variable K-Map

Don’t Care Conditions

In some situations, we don’t care about the value of a function for certain combinations of the variables.
In such situations we say the function is incompletely specified and there are multiple (completely specified) logic functions that can be used in the design.
we can choose to either cover or not cover the don’t care conditions

POS Form

The product of sums is the second standard form for Boolean expressions.
product-of-sums-expression = p-term . p-term… . p-term
p-term= literal +literal + ……. + literal
Example. (X+Y+Z )(X+Z)(X+Y)(X+Y+Z)
A maxterm is a product term that contains every variable, in complemented or uncomplemented form.
Example. in exp. above, X+Y+Z is a maxterm, but X+Z is not
A product of maxterms expression is a sum of products expression in which every term is a minterm.
Example. (X+Y+Z )(X+Y+Z)(X+Y+Z)(X+Y+Z) is sum of minterms expression that is equivalent to expression above.
Shorthand: List maxterms numerically. e.g. ∏M(1,3,6,7)

POSITIVE and NEGATIVE LOGIC

In positive logic systems, a high voltage is associated with logic 1, and a low voltage with logic 0.

sometimes it is more convenient to use the opposite convention
- In logic diagrams that use negative logic, a polarity indicator is used to indicate the correct logical interpretation for a signal.

LOGIC GATES

Posted on August 13, 2010 by masherz

LOGIC GATES

Boolean functions may be practically implemented by using electronic gates. The following points are important to understand.

Electronic gates require a power supply.
Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and 5V representing logic 0 and logic 1 respectively.
The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5V representing logic 0 and logic 1 respectively. In general, there is only one output to a logic gate except in some special cases.
There is always a time delay between an input being applied and the output responding.

TRUTH TABLE

Truth tables are used to help show the function of a logic gate.

AND GATE

OR Gate

NOT Gate

NAND Gate

NOR Gate

EXNOR Gate

EXOR Gate

The NAND and NOR gates are called universal functions since with either one the AND and OR functions and NOT can be generated.
A function in sum of products form can be implemented using NAND gates by replacing all AND and OR gates by NAND gates.
A function in product of sums form can be implemented using NOR gates by replacing all AND and OR gates by NOR gates.

Boolean Alebra & Functions

Posted on August 13, 2010 by masherz

Boolean Algebra & Functions

Basic rules of Boolean Algebra:

The basic rules for simplifying and combining logic gates are called Boolean algebra in honour of George Boole (1815 – 1864).

x · y = y · x

x + y = y + x

x · (y · z) = (x · y) · z

x + (y + z) = (x + y) + z

x · (y + z) = (x · y) + (x · z)

x + (y · z) = (x + y) · (x + z)

x · x = x

x + x = x

x · (x + y) = x

x + (x · y) = x

x · x’ = 0

x + x’ = 1

(x’)’ = x

(x · y)’ = x ‘ + y’

(x + y)’ = x’ · y’

Switching Theory & Logic Design

Posted on August 13, 2010 by masherz

Switching Theory & Logic Design

Switching theory and logic design provide mathematical foundations and tools for digital system design.
Digital circuits have become the standard for computing, control, and many other applications.
Any digital logic design can be created with three fundamental building blocks: